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EM83040A LCD CONTROLLER
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GENERAL DESCRIPTION
The EM83040A is a dot matrix LCD driver which is fabricated by low power CMOS technology. This chip includes 80- bits shift register , 80 bits data latch and 80 bits level driver. A LCD RAM inside can be mapping to LCD signal. It converts RAM data to parallel data and output lcd waveform to LCD.
FEATURES
(1) (2) (3) (4) (5) (6) (7) (8) (9) (10) (11) (12) Supply power 2.6~6V Internal RAM : 2.5k x 4 bits RAM can be controlled by eight signals including four bit data bus. LCD drive voltage :<13V Duty: 1/32, 1/48, 1/80 Build in DC converter double and triple Modularized function: connect to another 83040 to extent LCD matrix One DC converter enabled and other 83040 can shared with this. Internal regulator output for DC converter controlled by control register. (2.5V to 4.6V, 8 level) Chip form (EM83040AH), 128 pin package (14mmx20mm EM83040AAQ), 160 pin package (EM83040ABQ) Bias : 1/5 for 32 common, 1/7 for 48 common, 1/9 for 80 common. Fixed by internal circuit. Internal RC clock about 250 KHz.
APPLICATION
(1) (2) (3) Data Bank LCD toy Education computer
PIN ASSIGNMENTS
VREG
EM83040ABQ
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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O79 MAIN NC NC NC NC NC M1 VREG M0 EN RAMEN RAMADS RAMW RAMR RAMD3 RAMD2 RAMD1 RAMD0 LOAD VDD CA CB GND VSS2 VSS3 V1 V2 V3 V4 NC NC NC NC NC NC V5 O0
128 127 126 125 124 123 122 121 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103
102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65
O78 O77 O76 O75 O74 O73 O72 O71 O70 O69 O68 O67 O66 O65 O64 O63 O62 O61 O60 O59 O58 O57 O56 O55 O54 O53
EM83040AAQ
O52 O51 NC NC NC NC NC NC O50 O49 O48 O47 O46 O45 O44 O43 O42 O41 O40 O39 O38 O37 O36 O35 O34 O33 O32 O31 O30 P29 NC NC NC NC NC NC O28 O27
BLOCK DIAGRAM
O1 O2 O3 O4 O5 O6 O7 O8 O9 O10 O11 O12 O13 O14 O15 O16 O17 O18 O19 O20 O21 O22 O23 O24 O25 O26
39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64
VREG
V_BIAS M1,M0
MUX VSS2 or VSS3
Buffer1 Buffer2 Buffer3 Buffer4 Buffer5
MUX
:::::
BIAS
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
PIN DESCRIPTIONS
Symbol VDD GND VSS3 VSS2 MAIN I/O Power power power Power I
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Function Ground EN=0 and MAIN=1, 3*regulator output, EN=1 ,VSS3=VDD EN=0 and MAIN=1, 2*regulator output, EN=1, VSS2=VDD Master or slave control signal. MAIN=1 ,master unit MAIN=0 , slave unit This pin control whole chip power. This chip will work when this pin is connectted to ground. And whole chip will disable when connect to VDD voltage. EN=0 and MAIN=1 the chip will generate VSS2, VSS3, LOAD signal and internal RC clock. EN=1, standby mode Mode select Mode select RAM read and write control signal. 1 => can not read and write. 0=> can read and write. RAM data select signal 1=> RAM Data , 0=>Address RAM write signal, low write RAM read signal, low read RAM data or address bus LCD load signal between one COMMON signal to another . MAIN=1 , the master unit will output LOAD signal. MAIN=0 , the slave will accept the signal from master unit. regulator output, connect a capacitor to ground. Coupling capacitor Coupling capacitor Reference voltage input ,highest V1..lowest V5 LCD waveform output
EN
I
M1 M0 RAMEN RAMADS RAMW RAMR RAMD3~ RAMD0 LOAD
I I
I/O
VREG CA CB V1~V5 O1~O80
power I I I O
FUNCTION DESCRIPTIONS
(1)User can use MAIN pin to chose master unit or slave unit. MAIN 1 0 Unit MASTER SLAVE Function Generate these signals Load, VSS2, VSS3, Internal RC clock Accept these signals Load, V1, V2, V3, V4, V5
(2)User can use M1,M2 to chose four modes. As followed MASTER Mode1 Mode2 Mode3 Mode4 MAIN 1 1 1 1 M1 0 0 1 1 M0 0 1 0 1 Segment Reserved for test O(32:1)=S(32:1) O(48;1)=S(48:1) Common O(80:1)=C(80:1) O(80:33)=C(48:1) O(80:49)=C(32:1) Bias 1/9 1/7 1/5 5.31.2001
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* This specification are subject to be changed without notice.
EM83040A LCD CONTROLLER
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SLAVE Mode1 Mode2 Mode3 Mode4 MAIN 0 0 0 0 M1 0 0 1 1 M0 0 1 0 1 Segment Reserved for test O(80:1)=S(80:1) O(80:1)=S(80:1) O(80:1)=S(80:1) Common 1/9 1/7 1/5
* S=Segment, C=common * (M1, M0) for master must same as slave unit. (3)RAM control Writer mode
Fig.3 LCD RAM can be written or read with control signal. The RAMEN pin can select a RAM which can be read or write . The RAMADS pin can select whether RAMD(3:0) are data or address of RAM. At the address mode , RAMADS is low and user should sent address three times. From address (11:8) to address (3:0). Then it will go into data mode when RAMADS is high. In data mode , user can sent one or more nibble data which address can be increased by internal counter. Once the RAMEN pin is high, the RAM can not read and write.
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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Ten
RAMEN RAMADS RAMD(3:0) RAMW RAMR A3=address (11:8) A2=address(7:4) A1=address(3:0) ADDRESS A3 A2 A1 RAM enable RAM disable
DATA D1 D2
Tdd
D3
Tdh Tdv
Fig.4
As same as write mode , user has to sent address three times. And read data from RAM one by one which address can be increased by internal counter. NOTE!! Be sure to make RAMR low pulse 2 S (Tdv+data) width and 2 S (Tdd) high width at least. (5) RAM mapping RAM address is from 0 to address 2559 User fill "1" to LCD RAM , LCD driver will generate "light" waveform. Otherwise , it will generate a "dark" waveform. The LCD RAM area is mapped to segment 1 to segment 80 from address 0 to address 19. And user can refer to fig.5 to get the idea of LCD ram mapping. The other RAM can use as general RAM for data storage. And the RAM of address 2560 is a control register.
Address 2560 Control register
Address 2560 Control register
address2559 ...................
address2547 ......................................................................................................................... address2528
COM80
Area 11
EMPTY AREA
LCD RAM
Area 10
COM64
address2047 ................... : : : :
address2035 ......................................................................................address2019...............address2016
Area 9 Area 7
: :
: :
Area 8 Area 5
COM48
address1535 ................... : :
address1523 ............................................................address1511........................................address1504 :
Area 6
:
address1023 ................... : :
address1011 .......................address1003 ............................................................................. address0992
COM32
Area 4
Area 3
:
Area 2
:
Area 1
COM2 COM1
address0063 ................... address0031 ...................
address0051 ................... ..................................... .......................... ................................... address0032 address0019 ................... address0011................ address7........... address0003............... address0000
s80s79s78s77
s48
s32
s16
s4 s3 s2 s1
Fig.5
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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(6) LCD waveform
frame V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND V1 V2 V3 V4 V5 GND dark V1 V2 V3 V4 V5 GND light
com0
com1
com2
seg
seg
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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(7) Control register
Address 2560 Initial : 0000 Bit3 V_BIAS Bit2 Regulator2 Bit1 Regulator1 Bit0 regulator0
Bit2,1,0 : internal regulator output selection. (regulator2, regulator1, regulator0) (0,0,0) (0,0,1) (0,1,0) (0,1,1) (1,0,0) (1,0,0) (1,1,0) (1,1,1) Bit3 : internal Bias voltage selection (V_BIAS) 0 1 Bias fromV1 to V5 1/5 bias V_BIAS=0 V1 V2 V2 V2*4/5 V3 V2*3/5 V4 V2*2/5 V5 V2*1/5 *V2=VREG*2*97% *V3=VREG*3*95%
Output voltage 2.5V 2.8V 3.1V 3.4V 3.7V 4.0V 4.3V 4.6V
BIAS voltage VSS2 VSS3
1/5 bias V_BIAS=1 V3 V3*4/5 V3*3/5 V3*2/5 V3*1/5
1/7 bias V_BIAS=0 V2 V2*6/7 V2*5/7 V2*2/7 V2*1/7
1/7 bias V_BIAS=1 V3 V3*6/7 V3*5/7 V3*2/7 V3*1/7
1/9 bias V_BIAS=0 V2 V2*8/9 V2*7/9 V2*2/9 V2*1/9
1/9 bias V_BIAS=1 V3 V3*8/9 V3*7/9 V3*2/9 V3*1/9
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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ABSOLUTE MAXIMUM RATINGS
Rating Symbol Value Unit
DC SUPPLY VOLTAGE INPUT VOLTAGE OPERATING TEMPERATURE RANGE
V+ Vin Ta
<6 -0.5 TO Vdd 0.5 0 TO 70
V V C
DC ELECTRICAL CHARACTERISTICS (TA=0C ~ 70C, VDD=3V5%, VSS=0V)
Parameter Input High voltage Input Low current Output High current Input high voltage Standby current Output high voltage Sym. Min. VIH VIL IOH IOL ISD IOP 2.0 0.8 100 -100 1 130 4 160 Typ. Max. Unit V V A A A A VDD=3V VDD=3V EN=1 EN=0, MAIN =1(MASTER) , DC converter enable, INPUT=VDD 250kHz clock, No load EN=0 . MAIN =0 (SLAVE) , DC converter disable, INPUT=VDD 250kHz clock, No load Condition
40
70
A
Current of a buffer (V1 toV5) Voltage variation of regulator Regulator current Internal Bias resister
Ibuf 4 Vreg V-0.1 Ireg Rbias 1800
6 10 V V+0.1 10 15 2000 2200
A V A k
AC ELECTRICAL CHARACTERISTICS
Parameter RC clock variable Frame period Load period Enable time Write low pulse Data hold time Data to data time Data valid time Sym. Vrc Tframe Tload Ten Tw Tdh Tdd Tdv Min. -20 1/64 31 30 2 500 2 1500 Typ. Max. +20 Unit % S S S S nS S nS
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
AC TIMING
LCD control timing
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EN Tframe
FRAME LOAD C0 C1 POSITIVE FRAME NEGATIVE FRAME
Tload
CM C0
S0
S1
S2
S3
SN
Fig .7
LCD RAM write mode
Ten RAM enable RAMEN RAMADS RAMD(3:0) RAMW RAMR ADDRESS A3 A2 Tdh Tw A1 D1 Tdd D2 DATA D3
RAM disable
A3=address (11:8) A2=address(7:4) A1=address(3:0)
Fig .8 * This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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LCD RAM read mode
Ten RAMEN RAMADS RAMD(3:0) RAMW ADDRESS A3 A2
RAM enable
RAM disable
DATA A1 D1 Tdh Tdv D2
Tdd D3
RAMR A3=address (11:8) A2=address(7:0) A1=address(3:0) D1= first nibble D2=second nibble D3=third nibble data
Fig .9
APPLICATION CIRCUIT
(1) C32 x S48
VREG
Fig .10 * This specification are subject to be changed without notice. 5.31.2001
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EM83040A LCD CONTROLLER
(2) C32 x S128
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VREG
VREG
Fig .11 (3) C48 x S112
VREG
VREG
Fig .12 * This specification are subject to be changed without notice. 5.31.2001
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EM83040A LCD CONTROLLER
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(4) C80 x S160
VREG
VREG
VREG
Fig .13
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
PAD DIAGRAM
OP_79_ OP_78_ OP_77_ OP_76_ OP_75_ OP_74_ OP_73_ OP_72_ OP_71_ OP_70_ MAIN
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OP_69_ OP_68_ OP_67_ OP_66_ OP_65_ OP_64_ OP_63_ OP_62_ OP_61_ OP_60_ OP_59_ OP_58_ OP_57_ OP_56_ OP_55_ OP_54_ OP_53_ OP_52_ OP_51_
M1
155 VR1 M0 ENB RAMENB RAMADS RAMW RAMR RAMD_3_ RAMD_2_ RAMD_1_ RAMD_0_ LOAD VDD VCA VCB GND VR2 VR3 V1 V2 V3 V4 8 9 10 11 12 13
154 153 152 151 150 149 148 147 146 145 144 143 142 141 140 139 138 137 136 135 134 133 132 131 130 129 128 127 126 125 110 109 108 107 106 105 104 14 103 15 102 16 101 17 100 18 20 22 97 23 96 24 95 25 26 27 28 29 30 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 94 93 92 91 90 89 OP_37_ OP_36_ OP_35_ OP_34_ OP_33_ OP_32_ OP_31_ OP_30_ OP_29_ OP_40_ OP_39_ OP_38_ 99 98 OP_41_ OP_42_ OP_43_ OP_50_ OP_49_ OP_48_ OP_47_ OP_46_ OP_45_ OP_44_
(0,0)
V5
OP_0_
OP_1_
OP_2_
OP_3_
OP_4_
OP_5_
OP_6_
OP_7_
OP_8_
OP_9_
OP_10_
OP_11_
OP_12_
OP_13_
OP_14_
OP_15_
OP_16_
OP_17_
OP_18_
OP_19_
OP_20_
OP_21_
OP_22_
OP_23_
OP_24_
OP_25_
OP_26_
OP_27_
Chip Size : 3640 m x 2800 m Pad No. Sym. 8 VR1 9 M0 10 ENB 11 RAMENB 12 RAMADS 13 RAMW 14 RAMR 15 RAMD_3_ 16 RAMD_2_ 17 RAMD_1_ 18 RAMD_0_ 20 LOAD 22 VDD 23 VCA 24 VCB 25 GND 26 VR2 27 VR3 28 V1 * This specification are subject to be changed without notice. X -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 -1660.0 Y 1062.5 952.5 842.5 732.5 627.5 522.5 417.5 312.5 207.5 102.5 -2.5 -107.5 -212.5 -317.5 -422.5 -527.5 -632.5 -737.5 -842.5 5.31.2001
OP_28_
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EM83040A LCD CONTROLLER
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Pad No. Sym. 29 V2 30 V3 45 V4 46 V5 47 OP_0_ 48 OP_1_ 49 OP_2_ 50 OP_3_ 51 OP_4_ 52 OP_5_ 53 OP_6_ 54 OP_7_ 55 OP_8_ 56 OP_9_ 57 OP_10_ 58 OP_11_ 59 OP_12_ 60 OP_13_ 61 OP_14_ 62 OP_15_ 63 OP_16_ 64 OP_17_ 65 OP_18_ 66 OP_19_ 67 OP_20_ 68 OP_21_ 69 OP_22_ 70 OP_23_ 71 OP_24_ 72 OP_25_ 73 OP_26_ 74 OP_27_ 75 OP_28_ 89 OP_29_ 90 OP_30_ 91 OP_31_ 92 OP_32_ 93 OP_33_ 94 OP_34_ 95 OP_35_ 96 OP_36_ 97 OP_37_ 98 OP_38_ 99 OP_39_ 100 OP_40_ * This specification are subject to be changed without notice. X -1660.0 -1660.0 -1660.0 -1540.0 -1430.0 -1320.0 -1210.0 -1105.0 -1000.0 -895.0 -790.0 -685.0 -580.0 -475.0 -370.0 -265.0 -160.0 -55.0 50.0 155.0 260.0 365.0 470.0 575.0 680.0 785.0 890.0 995.0 1100.0 1205.0 1315.0 1425.0 1535.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 Y -952.5 -1062.5 -1172.5 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1240.0 -1120.0 -1010.0 -900.0 -790.0 -685.0 -580.0 -475.0 -370.0 -265.0 -160.0 -55.0 50.0 5.31.2001
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EM83040A LCD CONTROLLER
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Pad No. 101 102 103 104 105 106 107 108 109 110 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 Sym. OP_41_ OP_42_ OP_43_ OP_44_ OP_45_ OP_46_ OP_47_ OP_48_ OP_49_ OP_50_ OP_51_ OP_52_ OP_53_ OP_54_ OP_55_ OP_56_ OP_57_ OP_58_ OP_59_ OP_60_ OP_61_ OP_62_ OP_63_ OP_64_ OP_65_ OP_66_ OP_67_ OP_68_ OP_69_ OP_70_ OP_71_ OP_72_ OP_73_ OP_74_ OP_75_ OP_76_ OP_77_ OP_78_ OP_79_ MAIN M1 X 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1660.0 1535.0 1425.0 1315.0 1205.0 1100.0 995.0 890.0 785.0 680.0 575.0 470.0 365.0 260.0 155.0 50.0 -55.0 -160.0 -265.0 -370.0 -475.0 -580.0 -685.0 -790.0 -895.0 -1000.0 -1105.0 -1210.0 -1320.0 -1430.0 -1540.0 -1660.0 Y 155.0 260.0 365.0 470.0 575.0 680.0 785.0 895.0 1005.0 1115.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1240.0 1172.5
* This specification are subject to be changed without notice.
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EM83040A LCD CONTROLLER
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DESIGN NOTE : APPLICATION CIRCUIT WITH EXTERNAL CHARGE PUMP
* This specification are subject to be changed without notice.
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